As telecom service providers increasingly transition their circuit-switched transmission networks to a packet switched infrastructure to cater to an exponential growth in high-speed data services, the problem of efficiently supporting residual TDM services continues to be a challenge. Circuit Emulation technology enables such telecom operators to translate TDM signals such as E1/DS1, E3/DS3, STM-n/OC-n to appropriate packet formats and carry them on a modern packet transport network. An efficient implementation of circuit emulation requires the following:
The above requirements can only be achieved by guaranteeing adequate bandwidth, prioritization and buffering along the end-to-end path to minimize packet losses, delays or reordering.
Tejas Circuit Emulation Service (CES) cards have one of the most advanced implementations of the circuit emulation function in the industry today. Tejas supports one of the densest realizations of CES functionality that includes both structure-agnostic and structure-aware emulation services as per relevant ITU/IETF/MEF standards. Tejas implementations are fully interoperable with third-party standards-based offerings. Adaptive Clock Recovery (ACR) or Differential Clock recovery (DCR) is used for clock extraction. The CES module has a stable clock source with temperature controlled crystal oscillators. Tejas implementation of CESoPSN supports PCM30 and PCM31 framing of E1s with flexible and fully reconfigurable timeslots and the ability to raise alarms for E1s. Synchronization information of these packetized TDM signals is maintained and distributed end-to-end through packet-based methods or Synchronous Ethernet (SyncE) as defined in physical layer standards ITU G.8261 and ITU G.8262.